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 TOP2004 General GAL Problem
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PolyVinalDistillate

United Kingdom
5 Posts

Posted - 02/23/2008 :  09:18:48  Show Profile  Reply with Quote
Hello folks,

I recently aquired a TOP2004 programmer with the intention of writing to GAL16V8A and 20V8A chips from numerous manufacturers. Unfortunately it arrived through the post with the software CD cracked almost in two, so I had to search online for software. I installed V2.52 of TopWin when I found it, and tested the programmer on various chips, all of which were a success EXCEPT the GAL chips I bought it to program!

The Programmer version reports as 'TOP2004 v1.33', and I was wondering if anyone else has experience of this version of the programmer and GAL chips.

I understand from the forums that there are issues with the GAL22V10 fusemap, and that this is a software bug, however my problem is that I can read and erase GAL20V8A chips, but not write them, and I can read GAL16V8A chips (though the bitpattern moves around if the read button is pressed too much), but not erase OR write.

I have tried to solve this problem by looking for older software versions (none of which have worked) older USB driver versions (which have also not worked), and testing with a USB HUB in case the report of my USB power level being 10 was't right, and had no luck at all.

I don't think it's a power issue, as I can write eproms with no problem at all, and GALs require 'EDIT' to be pulled to VPP before their bitpattern can be read... This suggests to me perhaps there is a software problem in my version of the programmer, but I am now at a loss.

I would like to know if anyone else has experienced these problems with GAL chips and solved them, or if it's likely I have a damaged programmer (concidering it must've taken a knock to break the CD).

Any help would be greatly appreciated,
Thanks :)
Reply #1

PolyVinalDistillate

United Kingdom
5 Posts

Posted - 02/26/2008 :  10:59:56  Show Profile  Reply with Quote
A little more detail:

I've done some testing, and found that there are 2 separate problems affecting GAL20V8 and GAL16V8 respectively.

On the 20V8, it appears that the 16.5 V is selected correctly for read, however during programming it drops to 10 v. (the GAL programming spec I have would suggest this is very wrong). So during the erase and read, it holds the 16.5 V, but during the write, this drops to 10 V.

On the 16V8, the 16.5 V is selected correcly for read/write/erase, however the voltage never reaches the pin of the devide being programmed - possibly a dodgy transistor.

I have done a little probing on the PCB with a multimeter, and found that there is a CPLD used to select the voltage levels through a resistor network as a simple DAC at the bottom of the PCB. The IO outputs of the CPLD seem to sit at 1.27v or 0 v on the resistors, thereby controlling the VPP voltage:

| |
| Xilinx CPLD IO pins |
-----------------------
| | | | |
- - - - -
| | | | | | | | | |
| | | | | | | | | |
- - - - -
| | | | |
----+----+----+----
|
|
to PSU VPP ctrl


When programming the 20V8 however, the ouputs drop to 0.7v, and cause the VPP set voltage to drop from 16.5v to 10v. This strikes me as odd - I would expect the CPLD to have logic outputs, and not intermediate.. but I have been unable to trace the source of the 1.27v logic drive for the CPLD.

Any suggestions as to what might cause this voltage drop on the CPLD would be greatly appreciated, as this would solve my GAL20V8 problem.
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Reply #2

PolyVinalDistillate

United Kingdom
5 Posts

Posted - 02/26/2008 :  11:01:52  Show Profile  Reply with Quote
To see the schematic in the last post, it would seem you will have to paste it into notepad or something similar to view in monospace!
Sorry :)
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Reply #3

PolyVinalDistillate

United Kingdom
5 Posts

Posted - 02/27/2008 :  10:29:41  Show Profile  Reply with Quote
As a (probably) final update...

I have decided to void any warrentys on the programmer, and gone about its innards with a multimeter and a soldering iron. I have narrowed down the 2 problems previously discussed to one of 2 possible causes.

First, both the 20V8 and 16V8 problems are caused by the same issue, but the symptoms are *slightly* different for each, presumably due to inconsistant transistors on the pins of the ZIF socket.

When programming GALs, pin 2 must be raised to VPP to switch the GAL into programming mode. As the TOP2004 is a *universal* programmer, these pins (10 and 12 on the ZIF) are also connected through 510-ohm resistors to an FPGA so logic levels can be applied for other devices.

When VPP is applied to the GAL, the FPGA lines are set to 0v, therefore the 16.5v programming voltage sinks about 32 mA through the 510-ohm resistors to the FPGA.

Cutting the track to the FPGA from ZIF pin 10 allowed the programmer to successfully program a GAL20V8 as the 32 mA sink was removed, however the VPP still seems very unstable. I have had to add a resistor trimmer to the DAC voltage selector to up 16.5v to 17v to get 100% success rate when programming.

My suspicion is that the PSU in my TOP2004 is faulty and cannot provide the required current at 16.5v (though it works for 12v quite well). Either that, or there is a software issue, and the FPGA pins *should* be in Hi-Z before VPP is applied.

I have been unable to improve the supply after trying various inductors and capacitors in place of the components present, and have given up and settled for the addition of switches to enable/disable the FPGA connections to the ZIF. This has provided a bearable (if not wonderful) solution :)

And just to be sure - what I have done is probably not a good idea if you ever want to return your programmer to the manufacturer for repair!! (assuming they have such a service).
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Reply #4

ZLM

2926 Posts

Posted - 02/27/2008 :  23:04:14  Show Profile  Reply with Quote
Good work!
The TOP uses their "marginal voltage technology" to build the programmer. This is why many TOP programmers has similar voltage issue.

As to your "the FPGA pins *should* be in Hi-Z before VPP is applied.". Yes. by theory, it should be in Hi-Z. However, the 16.5V will kill that FPGA since it exceed the maximum it can take. To protect the FPGA, I think TOP put that pin to Lo to let the voltage drop in the safty range on that pin.
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